Non-volatile storage devices, such as flash memory devices, have enabled increased portability of data and software applications. For example, flash memory devices can enhance data storage density by storing multiple bits in each cell of the flash memory. To illustrate, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more. Electronic devices, such as mobile phones, typically use non-volatile storage devices, such as flash memory devices, for persistent storage of information, such as data and program code that is used by the electronic device. Advances in technology have resulted in increased storage capacities of non-volatile storage devices with reductions in storage device size and cost.
To correct data errors, a flash memory device may utilize an error correcting code (ECC) technique. For example, the flash memory device may encode user data using an ECC technique to generate encoded data, such as an ECC codeword. The encoded data may be stored at the flash memory device and may be decoded by a decoder of the flash memory device, such as in response to a request for read access to the data from a host device that accesses the flash memory device.
The flash memory device may use a low-density parity check (LDPC) decoding technique to decode the data. The LDPC decoding technique may use a parity check matrix to decode an ECC codeword, such as by multiplying the parity check matrix and the ECC codeword to generate “decoded” data. Because the ECC codeword includes parity bits that satisfy a set of parity equations specified by the parity check matrix, one or more bit errors in the ECC codeword can be corrected using the LDPC decoding technique.
An LDPC decoding operation may be performed (or represented) using variable nodes and check nodes. The variable nodes may represent bit values of the ECC codeword, and the check nodes may represent the parity equations of the parity check matrix. Each variable node may be connected to one or more of the check nodes. The connections between variable nodes and check nodes (or “constraints”) may represent the set of parity equations specified by the parity check matrix. If bit values of decoded data satisfy the set of parity equations, then the decoded data is “correct” (e.g., has been successfully decoded).
Latency associated with LDPC computations may be reduced by increasing a number of variable nodes that are processed in parallel at a decoder. Coding techniques such as quasi-cyclic (QC)-LDPC coding results in groups of variable nodes, where all variable nodes within a group have no interdependencies with each other and therefore may be processed in parallel with each other. Although parallelism increases as the size of the groups increases, the number of groups in a codeword decreases with increasing group size, which can weaken the error correction capacity of the encoding scheme.